U.S. Pat. No. 5,877,523 describes a semiconductor memory cell that is suitable for storing a plurality of bits. In the case of this cell, two floating gate electrodes separated from one another are situated at the ends of a channel region above two adjoining LDD regions of source and drain. A control gate electrode is present for driving purposes. Charges can be stored separately in the two floating gate electrodes in order to change the relevant programming state of the cell. In a central portion of the channel region, only the control gate electrode is situated above a dielectric layer on the semiconductor material.
German Patent No. 100 36 911 C2 (also U.S. Pat. No. 6,673,677) describes a method for fabricating a multi-bit memory cell that has separate portions of a storage layer, which are provided for charge trapping and are present in each case at the boundaries between source and drain, respectively, and the channel region. In the case of this method, a source region and a drain region are formed by introduction of dopant in a semiconductor body. A storage layer provided for the storage of charge carriers is arranged above the regions between boundary layers. It is possible for the storage layer to be a nitride, in particular, and for the boundary layers to be oxide. The storage layer is removed with the exception of regions situated at the boundary between the channel region and the source region and, respectively, at the boundary between the channel region and the drain region. Therefore, the storage layer is interrupted above a central portion of the channel region. This structure is fabricated by fabricating an auxiliary layer having a cutout in the region of the storage layer, and by fabricating spacers at the sidewalls of the auxiliary layer. The central portions of the storage layer are then removed between the spacers. Only then is the gate electrode fabricated and patterned.
Multi-bit flash memory cells have acquired increasing importance in the meantime. Instead of an interrupted storage layer, it is possible to use a continuous charge trapping layer, which is programmed and erased by local injection of charge carriers. In this case, however, the location of the charge stores is designed only by the mechanism of charge carrier injection, but not by the storage medium itself.
The publications in respect of the IEEE Nonvolatile Semiconductor Memory Workshop (NVSMW) 2003, in particular the paper by B. Hradsky et al., “Local Charge Storage in Silicon Nanocrystal Memories”, pp. 99–100, and the publication by S. Tiwari et al., “A silicon nanocrystals based memory”, Appl. Phys. Lett. 68, 1377–1379 (1996), describe semiconductor memories having memory cells with a storage medium comprising silicon nanocrystals between the gate electrode and the channel of a transistor structure.
U.S. Pat. No. 6,342,716 B1 describes memory cells containing nanocrystals for forming floating gate electrodes laterally with respect to the channel regions and at the sidewalls of the gate electrodes.